The present invention relates to a method and an apparatus for distributing clock signals to each of a plurality of devices incorporated into an electronic computer.
The electronic computer is provided with a plurality of devices. Each device executes processes while being synchronized by use of the clock signals. Employed in this case is a clock distributing apparatus for distributing the clock signals to the respective devices. Phases of the clock signals distributed to the devices shift due to a difference in length between connection lines connected to the clock distributing apparatus. Under such circumstances, a delay element incorporated into the clock distributing apparatus supplies each device with in-phase clock signals.
A known clock distributing apparatus is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 55-960. This clock distributing apparatus includes the delay element corresponding to each of a plurality of packages defined as the plurality of devices. Each delay element distributes the clock signals generated by a clock generating section to the respective packages with a predetermined quantity of delay.
At this time, a phase measuring section compares a phase difference between the clock signal generated by the clock generating section and the clock signal distributed to each package. The in-phase clock signal is supplied to each package. For this purpose, each delay element gives a delay quantity corresponding to the phase difference therebetween. That is, this clock distributing apparatus distributes the equiphase clock signals to the respective packages by automatically adjusting the delay quantities of the respective delay elements.
Further, another known clock distributing apparatus is disclosed in, e.g., Japanese Patent Laid-Open Publication No. 63-87015. This clock distributing apparatus includes a program delay element per package. Each program delay element selects a desired delay quantity from a plurality of delay quantities. Namely, the program delay element automatically adjusts the delay quantity of the clock signal, thereby reducing the number of adjusting steps for an optimum phase of the clock signal.
In the known clock distributing apparatuses, however, because of the delay element being provided per package, the number of delay elements increase with an increment in the number of packages. For this reason, the clock distributing apparatuses become intricate in terms of their configurations.
Moreover, when actually adjusting the phase of the clock signal, the phase measuring section measures the phase of the clock signal delayed by the delay element having a certain delay quantity. Based on this measured phase quantity, the delay element having a certain delay quantity is exchanged to the delay element adjusted to the optimum delay quantity. This therefore conduces to a problem of requiring a large number of adjusting steps.
Further, the another known clock distributing apparatuses includes the plurality of delay elements and a selecting circuit for selecting the plurality of delay quantities for every program delay element. For this reason, the configuration of the clock distributing apparatus becomes complicated.